The present invention relates to the manufacturing of semiconductor devices, and more particularly, to nickel silicide processes that prevent silicide shorting.
Over the last few decades, the semiconductor industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices, and the most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One silicon-based semiconductor device is a metal-oxide-semiconductor(MOS) transistor. The MOS transistor is one of the basic building blocks of most modern electronic circuits. Importantly, these electronic circuits realize improved performance and lower costs, as the performance of the MOS transistor is increased and as manufacturing costs are reduced.
A typical MOS semiconductor device generally includes a semiconductor substrate on which a gate electrode is disposed. The gate electrode, which acts as a conductor, receives an input signal to control operation of the device. Source and drain regions are typically formed in regions of the substrate adjacent the gate electrodes by doping the regions with a dopant of a desired conductivity. The conductivity of the doped region depends on the type of impurity used to dope the region. The typical MOS transistor is symmetrical, in that the source and drain are interchangeable. Whether a region acts as a source or drain typically depends on the respective applied voltages and the type of device being made. The collective term source/drain region is used herein to generally describe an active region used for the formation of either a source or drain.
MOS devices typically fall in one of two groups depending the type of dopants used to form the source, drain and channel regions. The two groups are often referred to as n-channel and p-channel devices. The type of channel is identified based on the conductivity type of the channel which is developed under the transverse electric field. In an n-channel MOS (NMOS) device, for example, the conductivity of the channel under a transverse electric field is of the conductivity type associated with n-type type impurities (e.g., arsenic or phosphorous). Conversely, the channel of a p-channel MOS (PMOS) device under the transverse electric field is associated with p-type impurities (e.g., boron).
A type of device, commonly referred to as a MOS field-effect-transistor (MOSFET), includes a channel region formed in the semiconductor substrate beneath the gate area or electrode and between the source and drain regions. The channel is typically lightly doped with a dopant having a conductivity type opposite to that of the source/drain regions. The gate electrode is generally separated from the substrate by an insulating layer, typically an oxide layer such as SiO2. The insulating layer is provided to prevent current from flowing between the gate electrode and the source, drain or channel regions. In operation, a voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode, a transverse electric field is set up in the channel region. By varying the transverse electric field, it is possible to modulate the conductance of the channel region between the source and drain regions. In this manner an electric field is used to control the current flow through the channel region.
The semiconductor industry is continually striving to improve the performance of MOSFET devices. The ability to create devices with sub-micron features has allowed significant performance increases, for example, from decreasing performance degrading resistances and parasitic capacitances. The attainment of sub-micron features has been accomplished via advances in several semiconductor fabrication disciplines. For example, the development of more sophisticated exposure cameras in photolithography, as well as the use of more sensitive photoresist materials, have allowed sub-micron features, in photoresist layers, to be routinely achieved. Additionally, the development of more advanced dry etching tools and processes have allowed the sub-micron images in photoresist layers to be successfully transferred to underlying materials used in MOSFET structures.
As the dimensions of the MOSFET shrinks, contacts and spacing between contacts also decrease in size, and increased performance requires that contact resistance remain relatively low. Contacts are formed after the source/drain regions have been formed within the semiconductor substrate of the MOSFET and the gate areas defined. An interlevel dielectric is then formed across the topography to isolate the gate areas and the source/drain regions. Interconnect routing is then placed across the semiconductor topography and connected to the source/drain regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric.
The entire process of making ohmic contacts to the impurity regions and/or the gate areas and routing interconnect material between the ohmic contacts is described generally as xe2x80x9cmetallizationxe2x80x9d. The term metallization is generic in its application, as conductive materials other than metal are commonly used for metallization. As the complexity of integrated circuits has increased, the complexity of the metallization composition has also increased, which leads to a further problem.
Metallization typically involves patterning a protective mask upon areas of the interlevel dielectric exclusive of where the ohmic contact is to be formed. The area of the interlevel dielectric left uncovered by the mask is then etched to form an opening or window directly above the source/drain regions and/or the gate areas to which contact is to be made. The contact window is then filled with a conductive material. A problem associated with this process is that the mask, and hence the contact, may be misaligned with the areas to which contact is to be made, resulting in increased resistance at that interface. Furthermore, aligning contact windows via a separate masking step makes minimizing the size of source/drain regions difficult.
Performance improvements have been obtained by solving the problems of increased resistance and misalignment through use of a salicide process (Self-ALIgned-siliCIDE). This process has become a mainstay in semiconductor processing because the process produces contacts having low-ohmic resistance and the contacts are formed using a self-aligned process.
A salicide process involves depositing a refractory metal across the semiconductor topography. After the refractory metal is deposited and subjected to high enough temperature, a silicide reaction occurs wherever the metal is in contact with a region heavily concentrated with silicon. In this manner, metal silicide may be formed exclusively upon the source/drain regions and the upper surface of a polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) gate conductor interposed between the source/drain regions. Silicide formation formed upon a polysilicon gate is generally referred to as polycide gate, which significantly reduces the resistance of the gate structure, as compared to previously used polysilicon gate structures. Silicide formation on the source/drain regions also significantly reduce the resistance of the contacts to the source/drain regions. Any unreacted metal is removed after formation of the silicide.
A number of different techniques and fabrication processes have been used to form MOSFET devices using the salicide process. With reference to FIGS. 1A-1I, one typical MOSFET fabrication process according to conventional techniques will be described. In FIG. 1A, separate MOSFET devices are separated on a silicon substrate 102 using isolation structures, such as a field oxide (not shown) or a shallow isolation trench 216. A shallow isolation trench 216, for example, can be formed by etching either isotropically with wet techniques or anisotropically with dry etch techniques. An oxide 218 is thereafter deposited within the trench 216. The oxide 218 is deposited such that an edge 220 of the oxide 218 meets the substrate 102 at what will later be lightly doped regions within the substrate 102. For purposes of clarity, the trench 216 and the oxide 218 are not shown in FIGS. 1B-1I.
In FIG. 1B, a gate oxide 104, formed from silicon dioxide, is formed on the top surface of the substrate 102 using thermal oxidation at temperatures from 700 to 1000xc2x0 C. in an oxygen atmosphere. After deposition of the gate oxide 104, a blanket layer of undoped polysilicon 106 is deposited, for example by low pressure chemical vapor deposition (LPCVD), on the top surface of gate oxide 104. The polysilicon layer 106 deposited on the substrate 102 can then be implanted with nitrogen ions, as depicted by arrows 160. The nitrogen ions are added to retard the diffusion of boron atoms.
In FIG. 1C, a photoresist 110 is deposited as a continuous layer on the polysilicon layer 106, and the photoresist 110 is selectively irradiated using a photolithographic system, such as a step and repeat optical projection system, in which ultraviolet light from a mercury-vapor lamp is projected through a first reticle and a focusing lens to obtain a first image pattern. The photoresist 110 is then developed and the irradiated portions of the photoresist are removed to provide openings in the photoresist 110. The openings expose portions of the polysilicon layer 106 which will thereby define a gate electrode.
In FIG. 1D, an anisotropic etch is applied to remove the exposed portions of the polysilicon layer 106 and the underlying portions of the gate oxide 104. After etching, the remaining portion of polysilicon layer 106 provides a polysilicon gate 112 with opposing vertical sidewalls (or, edges) 114, 116.
In FIG. 1E, the photoresist 110 is stripped, and lightly doped (LDD) source/drain regions 130, 132 are formed by an ion implantation, as represented by arrows 128. The ion implantation may be an n-type dopant, such as arsenic, if an NMOSFET is desired, or a p-type dopant, such as boron, if a PMOSFET is desired. The LDD source/drain regions 130, 132 are formed within the substrate 102 immediately adjacent to the sidewalls 114, 116 and are self-aligned with the polysilicon gate 112.
In FIG. 1F, sidewall spacers 162, 164 are formed following the implantation of the LDD source/drain regions 130, 132. The sidewall spacers 162, 164 may be silicon nitride or, alternatively, silicon oxide formed from material such as plasma-enhanced oxide (PEOX) or tetraethoxysilane (TEOS) oxide. The sidewall spacers 162 and 164 are formed immediately adjacent to the polysilicon gate 112 and over the substrate 102. After formation of the sidewall spacers 162, 164, heavily doped (HDD) source/drain regions 200, 202 are formed by a second ion implantation, as represented by arrows 204. The HDD source/drain regions 200, 202 are formed within the substrate 102 and extend past the LDD regions 130, 132 immediately adjacent to the sidewall spacers 162, 164. The sidewall spacers 162, 164 act as masks, which protect portions of the LDD regions 130, 132 from being heavily doped.
In FIG. 1G, a metal silicide is formed following the creation of the source/drain regions 130, 132. This process involves blanket depositing a layer of nickel 140, or other metals such as titanium and cobalt, over the polysilicon gate electrode 112 and the source/drain regions 130, 132 of the substrate 102. Although titanium and cobalt have been used to form silicide layers, nickel silicide (NiSi) has recently become a preferred silicide material for several reasons. An advantage of nickel silicide is that it can be rapidly formed at low temperature (400-600xc2x0 C.), making it suitable for low temperature processes in MOSFET fabrication. Other advantages of nickel silicide include no linewidth dependence, a reduction in xe2x80x9ccreep upxe2x80x9d phenomenon, low resistivity, a one-step anneal, a larger process window, and low silicon consumption. Yaozhi Hu and Sing Pin Tay, xe2x80x9cSpectroscopic Ellipsometry Investigation of Nickel Silicide Formation by Rapid Thermal Processxe2x80x9d, J. Vac. Sci. Technol. A 16(3), May/Jun 1998, 1820.
In FIG 1H, the nickel layer 140 is transformed into nickel silicide 142 by a one-step thermal process, which causes the underlying silicon substrate 102 or polysilicon gate electrode 112 to react with the nickel layer 140 to form nickel silicide 142. This thermal process is typically a rapid thermal anneal at temperatures of between about 350xc2x0 C. to 750xc2x0 C. A typical process is a 550xc2x0 C. anneal for about 40 seconds in a nitrogen atmosphere. The formation of nickel silicide begins at about 250xc2x0 C. when the nickel layer 140 reacts with silicon 102, 112 to form a Ni2Si film. With an increase in time or an increase in temperature to above 300xc2x0 C., the Ni2Si film reacts with the silicon 102, 112 to form the NiSi layer 142. The square of the thickness of the NiSi layer 142 varies linearly with time and the reaction proceeds until the Ni2Si film is totally consumed. P. Gas and F. M. d""Heurle, xe2x80x9cKinetics of Formation of TMM Silicide Thin Films: Self-diffusionxe2x80x9d, Properties of Metal Silicides, January 1995, 279.
In FIG. 1I, the nickel layer 140 over the sidewall spacers 162, 164 and the shallow isolation trench 216 is not reacted and can be removed easily. The unreacted nickel layer 140 can be removed, for example, using a H2SO4+H2O2 (2:1) mixture at a temperature of about 100xc2x0 C. Although NH4OH+H2O2 with deionized water is used for stripping silicide metals, such as with cobalt, titanium, or titanium nitride, this particular etch is not used with nickel. Nickel does not have a cap layer above the silicide metal, unlike the other materials, and removal of the cap layer is the main reason that NH4OH+H2O2 with deionized water is used for the other types of silicides.
A problem associated with this process is bridging, also known as silicide shorting. Bridging can arise when a silicide, such as nickel silicide, is formed between the silicon contact windows, such as between the gate electrode 112 and the source/drain regions 130, 132 arranged within the silicon substrate 102. The xe2x80x9cbridgexe2x80x9d between the gate electrode 112 and the source/drain regions 130, 132 creates a capacitive-coupled or fully conductive path, or xe2x80x9cshortxe2x80x9d between the gate electrode 112 and the source/drain regions 130, 132 and can lead to malfunction of the semiconductor device. As illustrated in FIG. 2, a common bridge 144 occurs when nickel silicide forms on the sidewall spacers 162, 164 between the gate electrode 112 and the source/drain regions 130, 132.
One mechanism in which a nickel silicide bridge 144 is formed on the sidewall spacers 162, 164 is by silicon atoms within the sidewall spacers 162, 164 diffusing into regions of nickel deposited over the sidewall spacers 162, 164, or vice versa. The silicon and nickel then react over or within the spacer regions during the rapid thermal annealing process, causing the nickel silicide to form on the sidewall spacers 162, 164.
Another mechanism that can cause bridging is significant thinning of the sidewall spacers 162, 164. Sidewall spacers 160, 162 serve to prevent the deposited nickel from contacting with, and hence reacting with, the polysilicon at the sidewall surfaces of the gate electrode 112. Without the sidewall spacers 162, 164, nickel silicide could form upon the sidewall surfaces of the gate electrode 112 and undesirably cause bridging between the gate electrode 112 and the source/drain regions 130, 132. Prior to metal deposition, native oxide on the exposed top surface of the gate electrode 112, as well as the top surface of the source/drain region 130, 132, is removed to allow for successful nickel silicide formation, as the native oxide will prevent the reaction between the nickel and the exposed silicon surfaces during annealing. The removal of the native oxide prior to metal deposition is typically performed using a buffered hydrofluoric acid procedure. However, this process can cause the sidewall spacers 162, 164 to be defective, or significantly thinned, thereby exposing the polysilicon of the gate electrode 112 and causing unwanted nickel silicide formation.
One technique of reducing unwanted nickel silicide formation in the sidewall spacer region is to lower the temperature at which the rapid thermal anneal takes place. At lower temperatures of about 380 to 420xc2x0 C., there is reduced diffusion of both nickel and silicon atoms. The disadvantage of using these lower temperatures for the rapid thermal anneal process, however, is that the lower temperature also lowers the growth rate of nickel silicide and therefore the processing time increases, which lowers throughput and increases the cost of processing. Accordingly, a need exists for an improved method of nickel silicide formation that reduces or eliminates bridging or silicide shorting and also allows for higher temperatures during the rapid thermal anneal process.
This and other needs are met by embodiments of the present invention which provide a method of manufacturing a semiconductor device that reduces or eliminates bridging over sidewall spacers. The method comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; forming nickel silicide layers disposed on the source/drain regions and the gate electrode, and two etching steps.
By providing two etching steps, a first etch can remove unreacted nickel over the sidewall spacers and the second etch can remove any nickel silicide formed on the sidewall spacers, thereby preventing malfunction of the semiconductor device from silicide shorting. Also, because the nickel silicide formed on the sidewall spacers will be subsequently removed, a higher temperature can be used during the rapid thermal anneal, which allows for greater throughput and lower costs of processing.
A further aspect of the present invention is that the first etch uses an etchant that exhibits a high selectivity to nickel and a low selectivity to nickel silicide, and the second etch uses an etchant that exhibits a high selectivity to nickel silicide. In current embodiments of the invention, the first etchant is a sulfuric peroxide mix and the second etchant is an ammonia peroxide mix. Furthermore, the nickel silicide layers are formed during a rapid thermal anneal at temperatures from about 380 to 600xc2x0 C.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.